L’Isep propose un Projet de Recherche Doctorale : Physics study of GaN based material normally off HEMT: linking material perspective to electrical behavior in real conditions
Informations générales
Venez nous rejoindre au Laboratoire d’Informatique, Signal & Image, Télécom & Electronique (LISITE)
situé à l’Isep, Ecole d’ingénieurs du numérique (Isep), 10 rue de Vanves à Issy-Les-Moulineaux en Ilede-France. https://www.isep.fr/la-recherche/
- Durée du programme : 36 mois maximum
- Domaine Sciences & Technologie de l’information & la communication
- Axe : Circuit intégré et système électronique
- Groupe de recherche : ECoS
- Collaboration Universidad San Francisco de Quito (USFQ)
Contexte et motivation scientifique
GaN alloys are among the III-V and wide band gap materials that intensively attract interest of the semiconductor industry [1]. Recently, material engineering has led researchers to prove the feasibility of normally off HEMT in GaN [2]. More precisely, 2 leads have been followed. The first focuses on gate stack engineering where solutions propose to artificially produce a positive-charge based current triggering. Among them, we can mention the Recessed gate structure [3], Fluorine implantation gate [4], or the p-(doped)GaN [5]. Others options focus on the HEMT architecture itself (e.g.: Hybrid drain gate injected transistor [6]) or the circuit topology [7]. Nonetheless these last options remain expensive and difficult to implement for mass production. Therefore, Gate stack engineering remains most interesting solution and the pGaN is among the most interesting options since it relies on relatively reliable and mature processing methods (MOCVD based epitaxy and ion implantation) [8] along with interesting electrical performance. Indeed, it was reported that pGaN technology can reach above 3KV breakdown voltage and enable low RON (bearing 10A) suitable for low to medium range power electronic applications [1]. Finally, the monolithic integration perspective opens the door to novel design approaches inspired by logic CMOS hence offering new application fields such as Power SoC [9].
However, this architecture faces many challenges. It was reported that such high power comes with limitations. Among them, it was reported that a self-limitation of the current intensity explained by a large increase in temperature degrades the device’s performance. Modelling has been proposed to consider this effect [10]. Threshold voltage instability has been evenly reported and has been explained by Reliability issues [11]. Finally, Breakdown voltage and electric field management by the architecture structure remains also an important challenge since power electronic applications keep exploring this tradeoff with form factors and scaling.
Finally, beyond power management, the time latency and frequency response remains not enough investigated with the pGaN while it remains interesting features.
To evaluate this last aspect, it is important to remember that the transport mechanism in GaN HEMT relies on quantum well which is modulated by piezo electric effect between the AlGaN/GaN barrier. This effect is well described but not completely understood in the frame of p-GaN gate stack and could be a limiting factor in very high frequency.
The GaN technology offers many advantage yet a unified model based on materials perspective including all this effect is missing and is essential to explore and investigate further the real potential of such technology. Such modelling will answer fundamental questions like: What is the link between charge defect and piezoelectric transport mechanism? How the temperature limitation caused by extreme dissipation effect in the quantum well could be clearly described. Further, the question of the Einstein relationship for mobility and the saturation velocity would be an interesting to explore for based GaN device.
Objectifs
- Produce an exhaustive state-of-the-art of the physics phenomenon governing the transport mechanism and the reliability effect on p-GaN
- Develop a material-centric modelling using TCAD calibrated with experimental p-GaN device (considering the question from the context)
- Design an analog circuit proving the frequency response of p-GaN technology device (an opamp for instance) up to the layout
Profil (connaissances et compétences attendues)
- Solid state physics (and specifically III-V material and semiconductor physics)
- Use of TCAD and Cadence (for a given PDK up to tape out)
- Coding in Verilog
- Basic of applied math and physics
- English (French or Spanish is a plus)
Niveau d’étude :
Equivalent to a Master degree according to Bolona agreement (Europe diploma), Master in Nanoelectronics or equivalent.
Contact & candidature
Any application must include:
- The diploma or certificate
- Transcript of the 2 last year
- CV
- Motivation letter
- Recommendation letter from a professor who taught to you in the field of physics
Please, send your application to:
Pr. Lionel Trojman, PhD-HDR : lionel.trojman@isep.fr
Wisly Fidel, PhD : wisly.fidel@isep.fr
Pr. Luis-Miguel Procel, PhD : lprocel@usfq.edu.ec
Bibliographie
[1] S. Musumeci and V. Barba, “Gallium Nitride Power Devices in Power Elec- tronics Applications: State of Art and Perspectives,” Energies, vol. 16, no. 9, p. 3894, May 2023.
[2] S. Chowdhury and U. K. Mishra, “Lateral and Vertical Transistors Using the AlGaN/GaN Heterostructure,” IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3060–3066, Oct. 2013.
[3] W. Saito, Y. Takada, M. Kuraguchi, K. Tsuda, and I. Omura, “Recessed-gate structure approach toward
normally off high-voltage algan/gan hemt for power electronics applications,” IEEE Transactions on Electron Devices, vol. 53, pp. 356–362, 2 Feb. 2006.
[4] Z. H. Zaidi, K. B. Lee, I Guiney, et al., “Enhancement mode operation in AlInN/GaN (MIS)HEMTs on Si substrates using a fluorine implant,” Semiconductor Science and Technology, vol. 30, no. 10, p. 105 007, Oct. 2015.
[5] I. Hwang, J. Oh, H. S. Choi, et al., “Source-Connected p-GaN Gate HEMTs for Increased Threshold Voltage,” IEEE Electron Device Letters, vol. 34, no. 5, pp. 605–607, May 2013.
[6] Y. C. Fong and K. W. E. Cheng, “Experimental study on the electrical characteristic of a GaN hybrid drain-
embedded gate injection transistor (HD-GIT),” in 2017 7th International Conference on Power Electronics Systems and Applications – Smart Mobility, Power Transfer & Security (PESA), IEEE, Dec. 2017, pp. 1–6.
[7] X. Huang, Z. Liu, Q. Li, and F. C. Lee, “Evaluation and Application of 600 V GaN HEMT in Cascode Structure,”
IEEE Transactions on Power Electronics, vol. 29, no. 5, pp. 2453–2461, May 2014.
[8] H. Liaw, R Venugopal, J Wan, R Doyle, P. Fejes, and M. Melloch, “GaN epilayers grown on 100 mm diameter si(111) substrates,” Solid-State Electronics, vol. 44, pp. 685–690, 4 Apr. 2000.
[9] N. Pozo, L.-M. Prócel, and L. Trojman, “All-gan integrated overcurrent pro- tection circuit using only
enhancement-mode p-gan devices,” in 2024 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI), 2024, pp. 1–
[10] G. Pavlidis, S. Pavlidis, E. R. Heller, E. A. Moore, R. Vetury and S. Graham, « Characterization of AlGaN/GaN HEMTs Using Gate Resistance Thermometry, » in IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 78-83, Jan. 2017, doi: 10.1109/TED.2016.2625264
[11] E. Acurio, F. Crupi, P. Magnone, L. Trojman, G. Meneghesso, F. Iucolano, On recoverable behavior of PBTI in
AlGaN/GaN MOS-HEMT, Solid-State Electronics, Volume 132, 2017, Pages 49-56, ISSN 0038-1101,
https://doi.org/10.1016/j.sse.2017.03.007