Title: Power Efficiency Optimization of Inductive Coupling Technology

Duration: From 5 months to 6 months

Description: The need of miniaturization leads to suppress the bulky battery in many electronic applications. There is a need to find alternative ways to power supply miniaturized devices. Inductive coupling technology is considered as a promising solution where energy is transfered wirelessly to the devices. However, the lifetime of the energy source is strongly affected by the poor efficiency of the system. The student will identity carrefully the parameter that could impact on the degradation of the power efficiency the inducting coupling link. He will also propose some solutions in order to optimize the power efficiency of the system. System-level design and simulations will be done to demonstrate and to validate the solutions.

Keywords: Inductive coupling, Power supply, Power efficiency, Power amplifier, Inductive antenna.

Techical skills required: Analog RF IC design, ADS.

Title: Contribution to the design of energetic efficient analog and RF Integrated Circuits

Duration: From 5 months to 6 months

Description: We are entering in the era of green electronics where high efficiency oriented electronic design is a growing subject. The student will bring its contribution to the study and the design of high efficient analog and RF integrated circuits (PA, LNA, VCO, PLL, Filter, ADC, DAC, OTA, ...) using Cadence and/or ADS RF Designer. The choice of the architecture and the design of the integrated circuit must take into account the imperfections in electronics (non-linearity, noise, ..) and/or reconfigurability considerations to target high performance, high efficiency, low power consumption.

Keywords: Analog RF IC design, High efficiency, Low power consumption.

Techical skills required: Analog RF IC design, CMOS technology, Cadence.

Contact: Dr. Francis Chan Wai Po ( Cette adresse email est protégée contre les robots des spammeurs, vous devez activer Javascript pour la voir. )

Title: FPGA - Hardware accelerator

Duration: 3 months

Description: The proposed project includes the following steps: Understand FPGA programming on manufacturer board; Program an hardware accelerator connected to an Avalon bus; Program the system to use the hardware accelerator.

Keywords: FPGA, Hardware accelerator, Digital electronics.

Technical skills required: Microprocessor programming, FPGA architecture.

Contact: Mr. Frédéric Amiel ( Cette adresse email est protégée contre les robots des spammeurs, vous devez activer Javascript pour la voir. )

Title: A power efficient MAC Layer processor solution for 3GPP LTE system.

Duration: 3 months

Description: We expect to design a reconfigurable and scalable hardware platform that provides the high performance and flexibility, but also real-time response capability with minimum power overhead. Some steps of work are planned. Firstly, characteristise the power consumption of MAC layer processor (at the algorithm level and RTL level). And secondly, design a low-power reconfigurable MAC layer processor.

Keywords: LTE, MAC layer, Reconfigurable processing.

Technical skills required: Microprocessor programming, Wireless comunications fundamentals.

Contact: Dr. Xun Zhang ( Cette adresse email est protégée contre les robots des spammeurs, vous devez activer Javascript pour la voir. )